A symmetrical high-voltage double-diffused drain device can be formed using the conventional MOS high-voltage integrated circuit (IC) technology. FIG. 1 shows such a MOS device 10. As shown in FIG. 1, MOS device 10 includes: a well region 100, a gate 101, a gate oxide 102, high-low-voltage gate oxide boundaries 103 and 104 symmetrically arranged at each of the two sides of the gate 101, heavily-doped regions 105 and 106 symmetrically arranged in source and drain respectively, lightly-doped regions 107 and 108 symmetrically arranged in source and drain respectively, contact holes 109 and 110 symmetrically arranged in source and drain respectively, and symmetrical shallow trench isolations 111 and 112.
The high-low-voltage gate oxide boundaries 103 and 104 are of an oxide-nitride-oxide (O—N—O) structure, which are used to prevent a low voltage region from being affected by the process of forming a high voltage region. For example, the high-low-voltage gate oxide boundary 103 includes two portions located at two sides of the heavily-doped region 105 horizontally, and a buffer oxide film 103a and a nitride film 103b vertically. The nitride film 103b is used to protect the low voltage region from over-loss of field oxide film and affecting the yield while removing the gate oxide in the low voltage region. The buffer oxide 103a is used for reducing the surface stress of the wafer and buffering the growth of the subsequent nitride film 103b. 
More specifically, if the distance between the contact hole 109 and the high-low-voltage gate oxide boundary 103 at one side of the gate 101 is C, the width of the high-low-voltage gate oxide boundary 103 at one side of the gate 101 is W, the distance between the gate 101 and the high-low-voltage gate oxide boundary 103 at one side of the gate 101 is S, and the width of the gate 101 is L, the device space (the distance between the source and drain contact hole 109 and 110) can be expressed as: L+2S+2W+2C.
Therefore, although the high-low-voltage gate oxide boundaries can protect the low voltage region from being affected by the process for forming the high voltage region during the fabricating process, the remaining high-low-voltage gate oxide boundaries at the heavily-doped region 105 and 106 and each of the two sides of the gate 101 may take extra space of the MOS device. With such limitation from the remaining high-low-voltage gate oxide boundaries, it may be difficult to narrow gaps between devices. Thus, it may be difficult to manufacture more devices using the fixed-size wafers, to increase the production efficiency and density of IC integration, or to reduce the cost.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.